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Calcolatori Elettronici

CFU: 9

Prerequisites

Basic language programming skills; fundamental algorithms for basic data structures.

Preliminary Courses

None

Learning Goals 

This course provides the methodological tools for the analysis and synthesis of basic machines for processing information (combinational and sequential logic networks). Students will learn to design fundamental machines. They will study the fundamentals of von Neumann architectures, the repertoire of operational codes and programming techniques in assembly language.

Expected Learning Outcomes 

Knowledge and understanding

The student must demonstrate knowledge and understanding of the problems related to the design of elementary machines with particular reference to basic machines for arithmetic applications and to more complex sequential machines (registers, counters, flip flops). He/she must also demonstrate knowledge of computer architectures and related subsystems, including processor main operations, memory communication methods, memory design and connection to various input and output devices.

Applying knowledge and understanding

The student must demonstrate to be able to design and develop elementary combinatorial networks, arithmetic combinatorial networks, sequential remainders. He/she must also be able to develop simple assembler programs for the management of elementary data structures (vectors, stacks,…).

Course Content - Syllabus

 

Analysis and synthesis of combinatorial networks. Minimization of fully or incompletely specified Boolean functions. Karnaugh maps. Quine-McCluskey method. Synthesis of combinatorial networks in NAND and NOR logic. Delays and hazards in combinatorial networks. Elementary combinatorial networks. Multiplexer and de-multiplexer. Encoder and decoder. Parity Checkers. Elementary arithmetic machines: adders, subtractors, comparators.

Analysis and synthesis of sequential networks. Models for the timing and structure of synchronous and asynchronous sequential networks. Flip-flop: general information, RS flip-flop with NOR gates. Flip-flop latch and edge-triggered. Flip-flop D. Switch flip-flop. Flip-flops T and JK. Registers. Serial and parallel registers. Shift registers.

Design methodology of synchronous networks. Synchronous and asynchronous counters. Sequence recognizers. Bus and transfers between registers.

The Processor: subsystems and architecture. The processor core components.  Processor algorithm. The role of the control unit. Accumulator processors and general register processors. Addressing techniques. Coding of instructions.

The central memory. Processor-memory interface. Organization of the memory system. Connecting memory modules. Static and dynamic RAM memories. Interconnection and bus systems. Mechanism of interruptions. Processor protections and controls. I / O management through polling and interruptions. The I / O subsystem.

Machine language and assembler language. Correspondence between high-level languages and machine language. Motorola 68000 processor assembly language. Assembly guidelines. Memory allocation of programs.

MC68000 processor simulator. Assembly and execution of assembler language programs. Assembler language subroutines. Techniques for passing parameters to procedures in machine language.

Readings/Bibliography

Textbook:

    Conte, Mazzeo, Mazzocca, Prinetto. Architettura dei calcolatori. Edizioni CittàStudi.

    Bolchini, C. Brandolese, F. Salice, D. Sciuto, Reti logiche, Apogeo Ed., 2008.

    B. Fadini, N. Mazzocca. Reti logiche: complementi ed esercizi. Liguori Editore, 1995.

Lecture notes and presentations provided by the teacher relating to theoretical and applicative topics.

Teaching Methods

The course includes about 70% of lectures in which theoretical topics are addressed, while the remaining 30% is reserved for practical lessons and exercises concerning the design and development of combinatorial and sequential machines; synchronous machines; and development of assembly programs.

Examination/Evaluation criteria

Exam type

The learning assessment includes first a written test with exercises on machine design and on assembly programs and then an oral discussion aimed at verifying the understanding of the theoretical concepts of the course.

 

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